Nanoimprint lithography is an embossing process whereby a stamp with a nanoscale pattern in its surface is pressed into a soft film on the surface of a semiconductor wafer.
The film is hardened, usually by heating or exposure to ultraviolet light, and the film retains the impressed pattern from the stamp.
The process is "astonishingly accurate", according to Nist, and can be used to create features as small as 10 nanometres across with relatively complex shapes.
Nist reported that nanoimprint lithography is emerging as a good candidate for building complex patterned insulating layers sandwiched between layers of logic devices in future generations of integrated circuits.
State-of-the-art semiconductors contain over a billion transistors packed into a footprint of silicon no bigger than a few square centimetres.
Several miles of nanoscale copper wiring are required to connect the devices, and these wires must be separated by a highly efficient insulator.
Materials scientists at Nist have already reported that nanoimprint lithography could be used on a functional insulating material to transfer patterns with details finer than 100 nanometres with minimal distortion due to the processing.
In a new paper to be published this month the scientists describe using a combination of techniques to measure the distribution of nanopores in the insulator material.
They found that the nanoimprint lithography embossing process actually has a beneficial effect in that it increases the population of small pores, which improve performance, reduces the population of larger pores that can cause problems and creates a thin, dense protective skin across the surface of the material.
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